Ring Counter: Wrong Feedback Stage Debug
A 4-bit ring counter circulates a single active bit through a series of flip-flops to create a sequential timing sequence.
Expected behavior:
| rst | Q3 | Q2 | Q1 | Q0 | |-------|------|------|------|------| | 1 | 0 | 0 | 0 | 1 | | 0 | 0 | 0 | 1 | 0 | | 0 | 0 | 1 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 0 | 1 | 0 |
Simulation shows the counter entering an incorrect sequence. After initialization to 0001, the next state is 0010, but the following state evaluates to 0101. The counter then oscillates between 0101 and 1010. The expected period of 4 is not achieved.
Inspect the circuit and correct the fault.
Constraints
- Do not add or remove any flip-flops.
- Modify only the incorrect wire connection causing the sequence failure.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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