Ring Counter: Invalid State Never Reaches Valid Sequence
A 4-bit positive-edge-triggered ring counter shifts its bit pattern one position to the right on every LOW-to-HIGH transition of CLK and feeds the least significant bit back to the most significant bit.
Five signals are shown: CLK (clock, period 2), and four outputs Q3 (most significant bit), Q2, Q1, and Q0 (least significant bit). The counter powers on in an invalid multi-hot state where Q3=1, Q2=1, Q1=0, and Q0=0.
Trace the outputs Q3, Q2, Q1, and Q0 across all 16 time steps to demonstrate that the counter loops indefinitely in a permanent invalid cycle without ever entering a valid one-hot state.
Constraints
- The next state of
Q2captures the current state ofQ3. - The next state of
Q1captures the current state ofQ2. - The next state of
Q0captures the current state ofQ1. - The next state of
Q3captures the current state ofQ0. - State transitions occur exactly on the LOW-to-HIGH edge of
CLKand remain stable until the next rising edge.
Topics
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