Ring Counter: Self-Correction for Any Invalid State
Multiphase clock generators and timing sequencers rely on ring counters to circulate a single active bit. Because standard ring counters cannot recover from glitch-induced invalid states, production designs require dedicated self-correction hardware.
The circuit must maintain a 4-bit ring counter that shifts right on every rising clock edge. If the current state Q is not strictly one-hot (meaning zero bits are HIGH, or two or more bits are HIGH), the circuit must synchronously force the next state to 1000. A synchronous load input is also provided to inject arbitrary states for testing.
| Current State (Q3 Q2 Q1 Q0) | load | Next State (Q3 Q2 Q1 Q0) | |-------------------------------------|--------|----------------------------------| | Any | 1 | D3 D2 D1 D0 | | 1000 | 0 | 0100 | | 0100 | 0 | 0010 | | 0010 | 0 | 0001 | | 0001 | 0 | 1000 | | All other states (Invalid) | 0 | 1000 |
Constraints
- Use standard D flip-flops for state storage.
- Implement synchronous state updates and self-correction exclusively on the rising edge of
clk. - Do not use pre-packaged counter or shift register components.
Topics
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