Blocking Assignment Race Condition
A two-stage pipeline synchronizer passes data between interconnected modules on the rising clock edge. Assume all registers initialize to 0.
Expected behavior:
| Cycle | D | Q1 | Q2 | |-------|-----|------|------| | 1 | 1 | 1 | 0 | | 2 | 0 | 0 | 1 | | 3 | 1 | 1 | 0 |
Simulation shows Q2 = 1 during cycle 1 when D = 1. The pipeline stage is being bypassed and the outputs are non-deterministic across different simulators. Inspect the circuit and correct the fault.
Constraints
- Use non-blocking assignments for sequential logic.
- Do not alter the module interface or port names.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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