Byte Serializer with Busy Flag
Serial communication interfaces like UART and SPI convert internal parallel data into a single-bit stream. The host system relies on a status flag to know when the transmitter is actively shifting data and cannot accept new input.
This circuit serializes an 8-bit input byte into a 1-bit output stream. On the rising edge of clk where Load is 1, the circuit captures DataIn and transitions to an active shifting state. Over the following 8 clock cycles, the captured byte is shifted out on Tx, starting with the most significant bit (bit 7) down to the least significant bit (bit 0).
The Busy output must assert to 1 on the first cycle of transmission and remain 1 exactly until the final bit has been transmitted.
| rst | State | Load | Next State | Busy | Tx | |-------|-------|--------|------------|--------|------| | 1 | Any | X | Idle | 0 | 0 | | 0 | Idle | 0 | Idle | 0 | 0 | | 0 | Idle | 1 | Shift 7 | 0 | 0 | | 0 | Shift | X | Shift n-1 | 1 | DataIn[n] |
Constraints
- Implement a synchronous active-high reset using the
rstsignal. - Ignore the
Loadsignal completely whileBusyis 1. - Output 0 on
Txwhenever the circuit is in the Idle state. - Transmit the byte strictly MSB-first.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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