Basic Serializer
High-speed interfaces like PCIe and USB rely on converting wide parallel data buses into single-bit streams to minimize pin count. The parallel-to-serial converter takes a multibit input and shifts it out one bit at a time over consecutive clock cycles.
The circuit must implement a 4-bit parallel-in, serial-out shift register. It uses an active-high load signal and a 4-bit data input D. When load is 1, the 4-bit input D is captured into the internal register. When load is 0, the register contents shift right by one position. The serial output Sout always reflects the least significant bit of the current internal register state.
| load | Next Register State | |--------|---------------------| | 1 | D[3:0] | | 0 | 0 concatenated with Reg[3:1] |
Constraints
- Implement a 4-bit internal register using synchronous flip-flops.
- Fill the most significant bit with 0 during a right shift.
- Route the least significant bit of the register directly to the
Soutport.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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