Circular Wait in Handshake Protocol
A DMA controller uses a valid-ready handshake protocol to transfer data to memory. The controller must assert valid when it has data, and the memory asserts ready when it can accept it.
Expected behavior:
When start is asserted, the DMA controller transitions to the transfer state and asserts valid. The memory responds by asserting ready. A successful transfer occurs when both valid and ready are high, after which the DMA asserts done.
Simulation shows a system deadlock on the first transfer attempt. When start is set to 1, both valid and ready remain 0 indefinitely, and done is never asserted. The DMA controller is incorrectly waiting for ready to be high before asserting valid, while the memory waits for valid to be high before asserting ready.
Inspect the circuit and correct the fault.
Constraints
- Do not change the memory controller logic.
- Modify only the DMA state machine logic to break the circular dependency.
Topics
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