Clock Gating with Test Enable Pin
Power-optimized ASICs aggressively shut down clocks to inactive blocks to save dynamic power. However, gating clocks during manufacturing tests prevents automatic test pattern generation (ATPG) tools from scanning data into downstream flip-flops.
The clock gating cell must pass the input clk to the output gclk when either the functional enable en or the test enable te is asserted. To prevent glitches on the clock line, the combined enable signal must be synchronized to the negative edge of clk before gating.
Assume en and te are stable before the rising edge of clk.
| clk | en | te | gclk | |-------|------|------|--------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 |
Constraints
- Implement a glitch-free clock gate using a negative-edge transparent latch and an AND gate.
- Combine the enable signals using a single OR gate before the latch.
- Do not use edge-triggered flip-flops for the gating logic.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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