Clock Loss Recovery Mux
A failover clock multiplexer switches system operation to a backup clock when the primary clock fails. The circuit selects clk_pri when sel_backup is 0, and cleanly transitions to clk_sec when sel_backup is 1.
Expected behavior:
Normal glitch-free switching occurs when both clocks are running. If clk_pri stops toggling while sel_backup is 0, asserting sel_backup to 1 must asynchronously force the multiplexer to release the primary clock and output clk_sec.
Simulation shows a lockup during the primary clock failure test. The test drives clk_pri to a constant 0, then asserts sel_backup to 1. The output clk_out remains flat at 0 instead of transitioning to clk_sec. The synchronization flip-flops in the primary domain never clear because their clock is dead.
Inspect the circuit and correct the fault.
Constraints
- Do not use combinational logic on the clock lines outside the dedicated output multiplexer gates.
- The switch to the backup clock must occur even if the primary clock is completely stopped.
- The design must remain glitch-free during normal switching when both clocks are active.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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