Clock Multiplexer Without Synchronization
A glitch-free clock multiplexer safely switches a single output clock between two asynchronous clock sources without generating runt pulses.
Expected behavior:
When Select is 0, ClkOut follows Clk0. When Select is 1, ClkOut follows Clk1. The transition between clocks must be clean and stable.
Simulation reports metastability warnings on the clock-gating latches when Select toggles asynchronously. The ClkOut signal occasionally propagates an undefined state during the clock switch. Inspect the circuit and correct the fault.
Constraints
- Do not remove the feedback paths between the two clock selection branches.
- You must use standard D flip-flops for synchronization.
- The output must remain glitch-free during any asynchronous transition of the select signal.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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