Closed-Loop MUX Synchronizer
Multi-bit binary data like performance counters or memory addresses cannot be passed across asynchronous clock domains using simple flip-flops due to bus skew. A closed-loop MUX synchronizer safely transfers arbitrary data by freezing the source, signaling the destination, and waiting for an acknowledgment.
When req_a asserts and busy_a is 0: 1. Latch the 8-bit data_a into a holding register and assert busy_a. 2. Toggle a control signal and synchronize it to clk_b using a 2-FF synchronizer. 3. When the synchronized signal toggles in domain B, capture the holding register into data_b and assert valid_b for exactly one clk_b cycle. 4. Synchronize the domain B control signal back to clk_a. 5. When the acknowledgment arrives in domain A, deassert busy_a.
Constraints
- Use standard D flip-flops and logic gates only.
- Do not route the multi-bit data bus through a synchronizer chain.
busy_amust remain high until the acknowledgment is received from domain B.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.