Combinational Logic Between Synchronizer Flops
A 2-stage synchronizer safely transfers an asynchronous signal into a new clock domain and provides an active-low output.
Expected behavior:
The path between the first and second synchronizer flip-flops must be a direct wire connection. This maximizes the time available for a metastable signal to settle. The output sync_out_n must reflect the inverted state of async_in after a two-cycle synchronization delay.
CDC linting reports a structural violation: combinational logic is detected between the synchronizer stages. The metastability resolution time is severely degraded.
Inspect the circuit and correct the fault.
Constraints
- Do not change the total number of flip-flops in the circuit.
- The final output must remain logically inverted relative to the synchronized input.
- The path between the two synchronizer flip-flops must contain no logic gates.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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