Combinational Loop via Implicit State
A logic unit within an arithmetic logic block computes a bitwise operation on inputs A and B based on a control signal Mode.
Expected behavior:
| Mode | A | B | Y | |--------|-----|-----|-----| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 |
Simulation shows incorrect outputs during test execution. For the input combination Mode=1, A=0, B=1, the output evaluates to 1. The expected output is 0. Inspect the circuit and correct the fault.
Constraints
- The circuit must remain purely combinational.
- Do not add sequential elements like flip-flops or explicit latches.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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