Combinational Output Causing Glitches
A clock gating enable signal is derived from state machine bits to control downstream logic power.
Expected behavior:
The output clk_en must be synchronized to the rising edge of clk to prevent combinational glitches during state transitions. It should evaluate to 1 when input A=1 and B=0 at the rising edge of clk and hold its value until the next clock edge.
Simulation shows clk_en = 1 immediately when A=1 and B=0, even while clk = 0. The waveform viewer shows spurious clock pulses because the enable signal changes state asynchronously. Inspect the circuit and correct the fault.
Constraints
- Do not change the input or output port names.
- The output must only update on the rising edge of
clk.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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