Counter from State Diagram: Implementation
Robust control units and sequencers must recover gracefully from single-event upsets. A state machine that explicitly defines transitions for all unused states guarantees deterministic recovery without hanging.
Implement a 3-bit synchronous counter that follows a 5-state sequence and forces all invalid states to return to zero. The state transition specification is defined below. Assume a synchronous reset signal rst that forces the state to 000.
| Current Q2 | Current Q1 | Current Q0 | Next Q2 | Next Q1 | Next Q0 | |--------------|--------------|--------------|-----------|-----------|-----------| | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 |
Constraints
- Use exactly three D flip-flops.
- Implement the next-state logic using basic combinational gates.
- Do not use asynchronous resets or presets to handle the invalid states.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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