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Codiode/Problems/Sequential Logic

Counter: Minimum Gate Correction for Single Self-Loop

HardLogic CircuitBuild

State machine lockups occur when noise flips register bits into an unmapped state that transitions to itself. Rather than redesigning the entire next-state logic block to handle this illegal state, engineers patch the specific node causing the self-loop to minimize area overhead.

A mod-7 counter for states 000 through 110 has a bug where state 111 loops indefinitely. The uncorrected next-state bit D2_in evaluates to 1 when the current state bits Q2, Q1, and Q0 are all 1. To break the loop without altering valid transitions, intercept D2_in and force the corrected output D2_out to 0 only when the counter is in state 111. For all other states, D2_out must exactly equal D2_in.

| Q2 | Q1 | Q0 | D2_in | D2_out | |------|------|------|---------|----------| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | 1 | | 0 | 0 | 1 | 0 | 0 | | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 1 | 1 | | 1 | 0 | 1 | 0 | 0 | | 1 | 0 | 1 | 1 | 1 | | 1 | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 |

Constraints

  • Combinational logic only.
  • Use a maximum of two logic gates to implement the correction.

Topics

FSMCountersState Correction

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