Counter: Recovery Within 1 Cycle vs. 2 Cycle Specification
Two positive-edge-triggered modulo-6 counters (A and B) normally count from 000 to 101 (0 to 5), but they handle the invalid state 110 (6) differently: Counter A recovers directly to 000 on the next clock edge, whereas Counter B transitions to 111 (7) before recovering to 000 on the subsequent edge.
Eight signals are shown: CLK (clock, period 2) FORCE_6 (synchronous input: when HIGH, forces both counters to 110 on the next rising clock edge) QA2, QA1, QA0 (Counter A outputs, initially 000) QB2, QB1, QB0 (Counter B outputs, initially 000)
Trace all six output signals across 12 time steps to verify their recovery behavior.
Constraints
- All state transitions are strictly synchronous and occur only on the LOW-to-HIGH transition of
CLK. - When
FORCE_6is LOW, the counters evaluate their current state to determine the next state.
Topics
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