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Codiode/Problems/Sequential Logic

BCD Counter: Self-Correction for All Six Invalid States

HardLogic CircuitBuild

Safety-critical instrumentation systems require counters that guarantee recovery from single-event upsets. The next-state logic of a robust BCD counter must not only count from 0 to 9, but also safely route any invalid state back to a known valid state immediately.

The circuit calculates the next state (D3, D2, D1, D0) based on the current state (Q3, Q2, Q1, Q0). During normal operation, it increments from 0000 to 1001 and wraps back to 0000. If the counter enters any of the six invalid states (10 through 15) due to a hardware fault, it must transition directly to 0000 on the next clock cycle.

| Q3 | Q2 | Q1 | Q0 | D3 | D2 | D1 | D0 | |------|------|------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |

Constraints

  • Implement the combinational next-state logic only.
  • Do not use don't-care optimization for states 10 through 15.
  • Route all invalid states explicitly to 0000.

Topics

BCDSequential LogicCountersState Machines

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