Counter: Recovery to Non-Zero Target State
Every robust hardware state machine requires a deterministic recovery path from unmapped states. In high-reliability protocols, a system catching a single-event upset must often transition to a specific active error-handling state rather than blindly resetting to zero.
Construct the next-state combinational logic for a 3-bit modulo-6 counter. The current state is provided via inputs Q2, Q1, and Q0. The circuit must drive the next state on outputs D2, D1, and D0. The valid sequence counts from 0 to 5 and wraps back to 0. If the counter enters an invalid state (6 or 7), it must immediately recover to state 5 on the next cycle.
| Q2 | Q1 | Q0 | D2 | D1 | D0 | |------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 | 0 | 1 |
Constraints
- Implement purely combinational logic.
- Do not use sequential elements like flip-flops or latches.
- Use only standard logic gates (AND, OR, NOT, XOR, NAND, NOR).
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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