Counter: Single Wrong Transition Diagnosis
A custom sequence counter controls the timing phases of a digital communication protocol. The counter must produce the continuous state sequence 3, 4, 5, 6, 7, repeating back to 3.
Expected behavior:
| Q2 | Q1 | Q0 | Next_Q2 | Next_Q1 | Next_Q0 | |------|------|------|-----------|-----------|-----------| | 0 | 1 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 1 | 1 | 0 | | 1 | 1 | 0 | 1 | 1 | 1 | | 1 | 1 | 1 | 0 | 1 | 1 |
Simulation shows the observed sequence is 3, 5, 4, 7, 6, 3. State 3 (011) incorrectly transitions to 5 (101). State 4 (100) incorrectly transitions to 7 (111).
Inspect the circuit and correct the fault.
Constraints
- Do not modify the clock or reset networks.
- Do not add additional flip-flops.
- Only replace or rewire the existing faulty logic gates.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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