Counter Wrapping at Wrong Value
Modulo counters provide exact division for digital clocks and frequency dividers. A modulo 10 counter increments its output Q from 0 to 9 on each active clock edge when en is high, and wraps back to 0.
Expected behavior:
| rst | en | Current Q | Next Q | |-------|------|-------------|----------| | 1 | X | X | 0 | | 0 | 0 | Q | Q | | 0 | 1 | 0 | 1 | | 0 | 1 | 8 | 9 | | 0 | 1 | 9 | 0 |
Simulation shows an incorrect state sequence. After reaching Q = 9 with en = 1, the next clock edge produces Q = 10 instead of wrapping to 0. The counter resets on the following cycle, creating an 11-state sequence. Inspect the circuit and correct the fault.
Constraints
- The circuit must use synchronous reset logic.
- Do not modify the clock distribution network.
Topics
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