Custom Even-Number Sequence Counter
Memory addressing schemes and specialized DSP algorithms often require non-linear or specific step-based data sequences. Generating a custom numeric progression directly in hardware avoids the latency of software-based lookup tables.
The circuit must generate a continuous 4-bit sequence of even numbers: 2, 4, 6, 8, 10. The sequence must wrap back to 2 on each active clock edge. Any invalid state must transition to the starting value of 2 (0010) on the next clock cycle. An active-high rst signal must asynchronously force the output to 2. The outputs Q3, Q2, Q1, and Q0 represent the current state, with Q3 as the most significant bit.
| Current State (Q3 Q2 Q1 Q0) | Next State (Q3 Q2 Q1 Q0) | |-------------------------------------|----------------------------------| | 0010 | 0100 | | 0100 | 0110 | | 0110 | 1000 | | 1000 | 1010 | | 1010 | 0010 | | All other states | 0010 |
Constraints
- Implement using D flip-flops and combinational logic gates.
- All invalid states must recover to
0010on the next clock edge. - The asynchronous
rstinput must immediately force the state to0010.
Topics
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