D Master-Slave Flip-Flop: Two D Latches Construction
Synchronous digital systems rely on edge-triggered elements to capture data at precise moments and prevent race conditions. The master-slave architecture constructs this edge-sensitive behavior by cascading two level-sensitive latches with opposite clock phases.
Construct a falling-edge-triggered D flip-flop using two D latches. The master latch must capture the input D while CLK is high. The slave latch must capture the master's output while CLK is low. The final output Q must only update its state when CLK transitions from 1 to 0. Implementations with swapped enables resulting in positive-edge behavior will fail verification.
| CLK_prev | CLK | D | Q | |------------|-------|-----|-----| | 0 | 0 | X | Q_prev | | 0 | 1 | X | Q_prev | | 1 | 1 | X | Q_prev | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 |
Constraints
- Use exactly two D latches and one NOT gate.
- Connect
CLKdirectly to the enable pin of the master latch. - Connect the inverted
CLKsignal to the enable pin of the slave latch. - Do not use any pre-built edge-triggered flip-flop components.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.