JK Flip-Flop with Asynchronous Preset and Clear
Commercial flip-flops require reliable startup states before the first clock edge arrives in the system. Active-low asynchronous preset and clear pins bypass the synchronous logic to initialize the output state immediately.
Implement a rising-edge triggered JK flip-flop with active-low asynchronous preset (PRE_bar) and clear (CLR_bar) inputs. The asynchronous controls must force the output state regardless of the clock signal. When both asynchronous controls are asserted simultaneously, both outputs are forced high, matching the standard 74LS76 specification.
| PRE_bar | CLR_bar | CLK | J | K | Q | Q_bar | |-----------|-----------|-------|-----|-----|-----|---------| | 0 | 1 | X | X | X | 1 | 0 | | 1 | 0 | X | X | X | 0 | 1 | | 0 | 0 | X | X | X | 1 | 1 | | 1 | 1 | ↑ | 0 | 0 | Q | Q_bar | | 1 | 1 | ↑ | 0 | 1 | 0 | 1 | | 1 | 1 | ↑ | 1 | 0 | 1 | 0 | | 1 | 1 | ↑ | 1 | 1 | Q_bar | Q |
Constraints
- Implement
PRE_barandCLR_baras true asynchronous controls that bypass the clock network entirely. - Do not route
PRE_barorCLR_barinto the synchronousJorKcombinational input paths. - Implement standard rising-edge triggered synchronous behavior when both asynchronous controls are inactive.
- Force both
QandQ_barto 1 whenPRE_barandCLR_barare simultaneously driven to 0.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.