D to JK Conversion: DFF from JK Flip-Flop
Standard cell libraries often use a universal flip-flop structure to implement various sequential elements. Converting a versatile JK flip-flop into a simple data latching mechanism allows for streamlined synchronous data storage.
The circuit must behave exactly like a positive-edge triggered D flip-flop using an underlying JK flip-flop. The output Q must follow the input D on every rising edge of the clock clk.
| D | Q_current | Q_next | |-----|-------------|----------| | 0 | 0 | 0 | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | 1 |
Constraints
- Use exactly one JK flip-flop.
- Use exactly one NOT gate.
- Do not use any other logic gates or sequential elements.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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