D to SR Conversion: SR Flip-Flop from DFF
ASIC libraries often contain a limited set of sequential primitives. Synthesizing arbitrary state elements requires mapping desired behavior onto available flip-flops using excitation tables.
Implement a positive-edge-triggered D flip-flop using a single SR flip-flop and basic combinational logic. The circuit must sample the D input on the rising edge of clk and update the output Q.
| D | Q (current) | Q (next) | |-----|---------------|------------| | 0 | 0 | 0 | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | 1 |
Constraints
- Use exactly one SR flip-flop.
- Use only combinational logic to drive the
SandRinputs. - Do not use any D flip-flops.
- The combinational logic must structurally guarantee that the forbidden state
S= 1 andR= 1 is never reached.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.