Data Changing Before Acknowledge Received
A clock domain crossing source interface must hold data stable on the bus until the destination domain acknowledges receipt.
Expected behavior:
When Send is asserted, the interface latches DataIn to DataOut and asserts Req. The DataOut bus must remain locked to this latched value until Ack is asserted, even if DataIn changes. Once Ack is received, Req deasserts.
Simulation shows DataOut changing while Req is high. Specifically, when Send triggers a transfer of DataIn = 5 and DataIn changes to 9 in the next cycle before Ack arrives, DataOut updates to 9. The data bus is not properly locked during the request phase. Inspect the circuit and correct the fault.
Constraints
DataOutmust be driven by a register that only updates when a new transfer is initiated.Reqmust remain asserted continuously untilAckis sampled high.
Topics
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