Debugging Array Bounds in N Stage Pipeline
Parameterized pipelines are used to delay signals by a configurable number of clock cycles to align parallel data paths. The circuit must shift an 8-bit input din through N register stages to produce the output dout.
Expected behavior:
For a configuration with 4 stages, the output dout must match din delayed by exactly 4 clock cycles.
Simulation shows dout = x at cycle 5 after din = 17 is applied at cycle 1. The final pipeline output is corrupted. Inspect the circuit and correct the fault.
Constraints
- The pipeline must remain parameterized and support any valid integer for the stage count.
- Do not change the module interface or port widths.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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