Debug: Lost MSB in Logical Shift Left
Serial protocols rely on shift registers to accurately assemble incoming data bits into parallel words. A 4-bit logical shift left circuit computes the next state by shifting a 4-bit input D one position to the left and appending a 1-bit serial input Sin to the lowest bit position.
Expected behavior:
| D (binary) | Sin | Q (binary) | |--------------|-------|--------------| | 0000 | 1 | 0001 | | 0001 | 0 | 0010 | | 0011 | 0 | 0110 | | 1000 | 1 | 0001 |
Simulation shows Q = 0111 for inputs D = 0011 and Sin = 0. The new least significant bit is incorrect. Inspect the circuit and correct the fault.
Constraints
- Do not modify the input or output pins of the circuit.
- Fix the wiring to correctly route the serial input.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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