Debug: Off By One Reset Condition
A modulo-5 counter tracks active cycles and wraps back to zero to manage repetitive timing events.
Expected behavior:
When Rst is 1, Q becomes 0 on the next clock edge. When En is 1, Q increments by 1. When Q reaches 4 and En is 1, Q must wrap around to 0 on the next clock edge.
Simulation shows Q = 5 after five consecutive cycles where En = 1. The output wrap condition triggers one cycle too late. Inspect the circuit and correct the fault.
Constraints
- The output port
Qmust remain 3 bits wide. - The counter must reset synchronously on the clock edge.
- The design must not use asynchronous clears for the wrap-around logic.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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