Debug: Ripple Counter Clock Cascading
Synchronous digital designs require all flip-flops to share a common clock to allow accurate static timing analysis and prevent routing congestion.
A 3-bit counter tracks system events and increments its outputs Q2, Q1, and Q0 on every rising edge of CLK when EN is high.
Expected behavior:
| EN | Q2 Q1 Q0 (current) | Q2 Q1 Q0 (next) | |------|--------------------------|-----------------------| | 0 | 0 1 1 | 0 1 1 | | 1 | 0 1 1 | 1 0 0 | | 1 | 1 1 1 | 0 0 0 |
Simulation shows timing violations and transient invalid states. On the test bench, transitioning from 011 to 100 produces intermediate glitch states 010 and 000 before settling, causing downstream logic to misfire. Inspect the circuit and correct the fault.
Constraints
- All flip-flops must be clocked directly by the primary system clock signal.
- Do not route flip-flop outputs into the clock pins of other flip-flops.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.