Debugging a Flush that Clears Too Much State
Pipeline flush logic clears invalid speculative instructions after a branch misprediction. The circuit computes the next-cycle valid bits (Next_V1, Next_V2, Next_V3) for a three-stage pipeline based on the current valid bits (V1, V2), incoming valid data (ValidIn), and a Flush signal.
Expected behavior:
| Flush | ValidIn | V1 | V2 | Next_V1 | Next_V2 | Next_V3 | |---------|-----------|------|------|-----------|-----------|-----------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 1 | 1 | 0 | | 0 | 1 | 1 | 1 | 1 | 1 | 1 | | 1 | 1 | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
When Flush is 0, valid bits advance normally: Next_V1 takes ValidIn, Next_V2 takes V1, and Next_V3 takes V2. When Flush is 1, the two most recent speculative stages (Next_V1 and Next_V2) must be cleared to 0. The oldest stage (Next_V3) holds committed data and must not be affected by the flush condition.
Simulation shows Next_V3 = 0 when V2 = 1 and Flush = 1. The flush is destroying valid committed data in the third stage. Inspect the circuit and correct the fault.
Constraints
- Do not modify the logic computing
Next_V1orNext_V2. - Ensure
Next_V3strictly follows the expected pipeline advancement rules without being cleared by the flush.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.