Debugging Lost State During Stall
A pipelined datapath must preserve in-flight data when downstream components are not ready. This single-stage pipeline registers data_in and valid_in when stall is low, and holds its current state when stall is high.
Expected behavior:
When stall is asserted, the outputs data_out and valid_out must remain frozen at their current values. New inputs are ignored until stall is deasserted.
Simulation shows that data is lost during a pipeline stall. When a valid input is followed by a cycle where stall = 1, the pipeline overwrites the stored data with the new input instead of holding the previous value. For example, if data_out = 5 and stall = 1 is asserted, the next cycle shows data_out incorrectly changing to the new data_in value. Inspect the circuit and correct the fault.
Constraints
- Do not add new registers or pipeline stages.
- Only modify the enable logic of the existing pipeline registers.
- The fix requires changing exactly one logic gate or wire connection.
Topics
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