Debugging Stale Forwarding Data
A pipeline forwarding unit resolves data hazards by bypassing results from the memory stage to the execution stage.
Expected behavior:
The unit outputs MEM_Data to Fwd_Data if the execution source register EX_Rs matches the memory destination register MEM_Rd and the memory stage data is valid (MEM_Valid = 1). Otherwise, it outputs the default register data Reg_Data.
Simulation shows Fwd_Data = 7 when EX_Rs = 2, MEM_Rd = 2, MEM_Valid = 0, MEM_Data = 7, and Reg_Data = 3. The circuit incorrectly forwards stale data from an invalid pipeline bubble instead of outputting the expected 3.
Inspect the circuit and correct the fault.
Constraints
- Do not change the input or output port names.
- Only modify the select logic feeding the forwarding multiplexer.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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