Debugging Unbalanced Parallel Paths
A pipelined arithmetic unit computes the expression (A * B) + C using a three-cycle multiplier and a one-cycle adder.
Expected behavior:
When inputs A, B, and C are provided at cycle T, the output Result at cycle T+4 must equal (A * B) + C.
Simulation shows incorrect results when input C changes during the multiplier calculation. For a test sequence where A=2, B=3, C=1 at cycle 0, followed by A=0, B=0, C=5 at cycle 1 and C=0 thereafter, the circuit outputs Result = 6 at cycle 4. The expected output is Result = 7.
Inspect the circuit and correct the fault.
Constraints
- Do not change the latency of the multiplier or the adder.
- The total pipeline latency must remain exactly 4 clock cycles.
Topics
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