Delayed Valid Signal in Pipeline
A pipelined data path processes incoming data over two clock cycles and asserts a valid flag when the result is ready. The DataOut and ValidOut signals must arrive in the exact same clock cycle to ensure the downstream receiver captures the correct payload.
Expected behavior:
| Cycle | DataIn | ValidIn | DataOut | ValidOut | |-------|----------|-----------|-----------|------------| | 0 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | | 2 | 0 | 0 | 1 | 1 | | 3 | 0 | 0 | 0 | 0 |
Simulation shows a timing misalignment during testing. When ValidIn and DataIn are asserted in cycle 0, DataOut correctly outputs the data in cycle 2, but ValidOut remains 0. The ValidOut signal erroneously asserts in cycle 3. The receiver captures garbage data from cycle 3 instead of the actual payload.
Inspect the circuit and correct the fault.
Constraints
- Do not alter the data path logic or its registers.
- The control path latency must perfectly match the data pipeline depth.
- Use only standard D flip-flops for the delay stages.
Topics
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