Delaying a Wide Bus vs Control Signal
High-performance digital pipelines often require synchronizing a wide data bus with a control signal that takes a longer path through the system. If an engineer naively passes a 32-bit data bus through a 16-stage pipeline to delay it, synthesis tools will instantiate 512 discrete flip-flops. This brute-force approach wastes massive amounts of silicon area and power. A vastly superior architectural pattern is to delay a 1-bit capture signal using 16 flip-flops, and use it to manage a small memory structure like a circular buffer or LUT-RAM for the data bus.
The bus_delay_optimizer module receives a 32-bit data_in bus and a 1-bit valid_in signal. It must output valid_out and data_out exactly 16 clock cycles later. If valid_in is asserted at clock cycle T, valid_out must be asserted at clock cycle T+16, and data_out must exactly match the data_in sampled at cycle T. When valid_out is low, data_out must be driven to 0.
| Signal | Direction | Width | Description | |-------------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all internal state and outputs go to 0 | | valid_in | input | 1 | Indicates data_in is valid and must be captured | | data_in | input | 32 | Data bus to be delayed | | valid_out | output | 1 | Asserted exactly 16 cycles after valid_in was asserted | | data_out | output | 32 | Delayed data; must be 0 when valid_out is 0 |
Constraints
- The module must delay valid data by exactly 16 clock cycles.
data_outmust output exactly 32'h00000000 on any cycle wherevalid_outis 0.- The reset signal
rst_nis asynchronous and active-low. - All outputs and internal tracking state must immediately reset to 0 when
rst_nis asserted.
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