DFF: Clock and Data Inputs Swapped Debug
A standard positive-edge-triggered D flip-flop captures the data input on the rising edge of the clock signal to synchronize data transfers between digital domains.
Expected behavior:
The output Q updates to match the input D exclusively on the low-to-high transition of CLK. At all other times, Q holds its previous state.
Simulation shows Q transitioning when D changes from 0 to 1, while CLK transitions have no effect on the output. The flip-flop captures state on the wrong signal edge. Inspect the circuit and correct the fault.
Constraints
- Do not replace the D flip-flop component.
- Only rewire the existing connections to resolve the fault.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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