Digital Hysteresis Filter
Noisy analog signals digitized by an ADC often hover around a single threshold, causing rapid and unwanted toggling in downstream logic. A digital hysteresis filter applies Schmitt trigger behavior in the digital domain to create a wide, stable deadband.
The circuit receives a 4-bit unsigned input val. The output y asserts high when the input reaches an upper threshold, and asserts low when it falls to a lower threshold. For values inside the deadband, y retains its previous state. The system is synchronous to the rising edge of clk.
| rst | val | Current y | Next y | |-------|-------------|-------------|----------| | 1 | X | X | 0 | | 0 | >= 12 | X | 1 | | 0 | <= 4 | X | 0 | | 0 | 5 to 11 | 0 | 0 | | 0 | 5 to 11 | 1 | 1 |
Constraints
- Use a synchronous, active-high reset.
- Trigger all state updates on the rising edge of the clock.
- Output
ymust strictly be 1-bit.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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