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Codiode/Problems/Sequential Logic

Early Reset Debouncer

HardLogic CircuitBuild

Mechanical switches and noisy communication lines produce rapid voltage spikes before settling. A robust debouncer prevents false triggers by requiring a continuous, unbroken period of stability before registering a state change.

The circuit monitors the noisy input din. If din changes state, the internal counter resets to zero immediately. Output dout updates to the value of din only after din remains stable for 4 consecutive clock cycles. Once dout updates, it holds that value until din stabilizes at a new value for 4 continuous clock cycles. Any glitch or premature transition on din must clear the stability count entirely.

Constraints

  • Implement using standard flip-flops and combinational logic.
  • Reset the internal counter synchronously on any cycle where the current din differs from the previous din.
  • Do not use high-level delays or behavioral wait statements.

Topics

sequentialdebouncernoise-filtering

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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