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Codiode/Problems/Sequential Logic

Counter Based Debouncer

MediumLogic CircuitBuild

Mechanical switches and buttons exhibit physical bounce, causing rapid spurious transitions before settling. While shift registers can filter this noise, they waste flip-flops for long debounce periods, making counter-based debouncers the standard for resource-efficient input conditioning.

The circuit must track the difference between the incoming noisy_in signal and the current clean_out state. When noisy_in differs from clean_out, an internal 2-bit counter increments on each active clock edge. If noisy_in matches clean_out at any point, the counter immediately resets to zero. When the counter reaches its terminal count of 3, clean_out updates to match noisy_in on the next clock edge, and the counter resets.

| Cycle | noisy_in | clean_out (current) | Counter Action | clean_out (next) | |-------|------------|-----------------------|----------------|--------------------| | 1 | 1 | 0 | 0 -> 1 | 0 | | 2 | 1 | 0 | 1 -> 2 | 0 | | 3 | 0 (bounce) | 0 | 2 -> 0 | 0 | | 4 | 1 | 0 | 0 -> 1 | 0 | | 5 | 1 | 0 | 1 -> 2 | 0 | | 6 | 1 | 0 | 2 -> 3 | 0 | | 7 | 1 | 0 | 3 -> 0 | 1 |

Constraints

  • Implement an internal 2-bit counter.
  • Use a synchronous active-high rst signal to clear the counter and clean_out to zero.
  • Update clean_out only when the counter reaches a value of 3.
  • Clear the counter to 0 immediately when noisy_in equals clean_out.

Topics

Sequential LogicCountersState MachinesDebouncer

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