Symmetric Shift Register Debouncer
Mechanical switches and buttons exhibit physical bounce upon both actuation and release, requiring robust digital filtering before interfacing with synchronous logic. A symmetric debouncer ensures clean transitions by waiting for the line to settle completely in either direction.
The circuit samples din on every rising clock edge into a 4-bit history sequence. The output dout must transition to 1 only after observing four consecutive 1s on din. It must transition to 0 only after observing four consecutive 0s on din. For any mixed sequence of inputs indicating ongoing bounce, dout must hold its previous state.
| din_3 | din_2 | din_1 | din_0 | dout_next | |---------|---------|---------|---------|-------------| | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 1 | | 1 | 0 | 1 | 1 | dout | | 0 | 0 | 1 | 0 | dout |
Constraints
- Implement a 4-bit shift register to capture the history of
din. - Use a synchronous reset
rstto clear all shift register bits anddoutto0. - Update
doutonly when the shift register contains exactly1111or0000.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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