Shift Register Debouncer
Mechanical switches physically bounce upon closure, generating a rapid sequence of false logic transitions. A sampling window filters these transients to present a clean, stable signal to downstream logic.
The circuit continuously samples the raw input btn_in on the rising edge of clk. The output btn_out asserts high if and only if the four most recent samples of btn_in are all logic 1. If any of the last four samples are logic 0, btn_out remains 0. The shift register must clear all stored history when rst is asserted high.
| rst | btn_in history (oldest to newest) | btn_out | |-------|-------------------------------------|-----------| | 1 | X X X X | 0 | | 0 | 0 1 1 1 | 0 | | 0 | 1 0 1 1 | 0 | | 0 | 1 1 1 1 | 1 |
Constraints
- Implement a 4-bit shift register using D flip-flops.
- Drive all flip-flops with the same
clksignal. - Clear all flip-flop states synchronously when
rstis high.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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