Maskable Edge Detector
Interrupt controllers and peripheral interfaces must precisely identify signal transitions while maintaining the ability to ignore them when busy. A maskable edge detector captures rising edges on an input line but suppresses the output if the channel is disabled.
The circuit must assert pulse high for exactly one clock cycle when din transitions from 0 to 1, provided en is 1 during the transition. If en transitions from 0 to 1 while din is already 1, pulse must remain 0.
| Cycle | en | din | pulse | Notes | |-------|------|-------|---------|-------| | 1 | 1 | 0 | 0 | Stable low | | 2 | 1 | 1 | 1 | Valid rising edge | | 3 | 1 | 1 | 0 | Remains high: no pulse | | 4 | 0 | 0 | 0 | Masked | | 5 | 0 | 1 | 0 | Masked rising edge | | 6 | 1 | 1 | 0 | Unmasked while high: no pulse |
Constraints
- Use D flip-flops to retain the previous state of the input.
- Gate the detection logic using combinational gates.
- Do not use asynchronous resets or clock gating to implement the enable functionality.
- Ensure the output is strictly synchronous.
Topics
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