Delayed Edge Detector
Communication interfaces often require waiting for data lines to settle before triggering a capture event based on a control signal transition. A delayed edge detector aligns the trigger pulse with this downstream pipeline delay.
The circuit must monitor the input d for a rising edge. When a low-to-high transition occurs, the output pulse must assert high for exactly one clock cycle. This pulse must occur exactly two clock cycles after the physical edge arrives, which is one cycle later than a standard synchronous edge detector.
| Cycle | d | pulse | |-------|-----|---------| | 1 | 0 | 0 | | 2 | 1 | 0 | | 3 | 1 | 1 | | 4 | 1 | 0 | | 5 | 0 | 0 |
Constraints
- Use standard D flip-flops for all sequential logic.
- Detect only rising (low-to-high) transitions.
- The
pulseoutput must be exactly one clock cycle wide.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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