Divide by 3 with 33 Percent Duty Cycle
Deriving specific baud rates or interface frequencies from a master oscillator often requires odd-modulo clock division. A divide-by-3 circuit with a 33 percent duty cycle generates a periodic signal that remains active for exactly one clock period out of every three.
Construct a finite state machine that divides the input clock clk by 3. On every rising edge of clk, the state machine must advance. When the synchronous reset rst is high, the circuit must reset and drive clk_out to 0. When rst is lowered, clk_out must output 1 on the first active clock edge, followed by 0 for the next two active clock edges. This 3-cycle pattern repeats indefinitely.
| Clock Cycle (post-reset) | rst | clk_out | |--------------------------|-------|-----------| | 0 (Reset active) | 1 | 0 | | 1 | 0 | 1 | | 2 | 0 | 0 | | 3 | 0 | 0 | | 4 | 0 | 1 | | 5 | 0 | 0 |
Constraints
- Implement the design using D flip-flops and combinational logic gates.
- Use a synchronous active-high reset.
- The output
clk_outmust be driven directly by a register to prevent combinational glitches.
Topics
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