Early Read from Synchronous RAM
A FIFO controller interfaces with a synchronous RAM block to buffer data transfers. It asserts rd_en and provides rd_addr to fetch data, passing the RAM output ram_rdata to the bus as bus_wdata.
Expected behavior:
When rd_en is asserted on clock cycle N, the synchronous RAM returns data on cycle N+1. The controller must assert bus_wvalid and drive bus_wdata on cycle N+1 to match the RAM read latency.
Simulation shows bus_wdata presenting the previous cycle's data when bus_wvalid is asserted. The valid signal is being driven high on cycle N instead of cycle N+1. Inspect the circuit and correct the fault.
Constraints
- Only modify the controller logic.
- Do not alter the synchronous RAM macro.
- Do not add extra wait states that reduce sequential read throughput.
Topics
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