Exhaustive Combinational Testbench
Exhaustive testing guarantees 100 percent coverage for small combinational blocks. Instead of writing manual test vectors, verification engineers write automated stimulus generators that iterate through the entire input space and compute the expected results for a self-checking testbench.
Design a hardware stimulus and expected-response generator for an 8-to-3 priority encoder. The module contains an 8-bit counter representing the test vector. When enabled, it increments this test vector to sweep through all 256 possible values. For the current test vector, it continuously outputs the expected 3-bit encoded value (the index of the highest set bit) and a valid flag (1 if any bit is set, 0 otherwise). Once all 256 values have been generated, it flags completion and halts.
Timing and Reset Rules: • Clock edge: posedge clk • Reset: Asynchronous, active-low (rst_n) • On reset, dut_in goes to 8'h00 and done goes to 1'b0. The combinational outputs expected_out and expected_valid must immediately reflect the reset value of dut_in. • When en is 1 and done is 0, dut_in increments by 1 on each clock edge. • When en is 0, dut_in holds its current value. • When dut_in reaches 8'hFF (255) and en is 1, on the next clock edge dut_in wraps to 8'h00 and done is set to 1. • When done is 1, the generator halts. dut_in stays at 8'h00 and done stays 1, regardless of en, until a reset occurs.
Worked Trace: Cycle 1: rst_n=0 → dut_in=0, expected_out=0, expected_valid=0, done=0 Cycle 2: rst_n=1, en=1 → dut_in=1, expected_out=0, expected_valid=1, done=0 Cycle 3: en=1 → dut_in=2, expected_out=1, expected_valid=1, done=0 Cycle 4: en=0 → dut_in=2, expected_out=1, expected_valid=1, done=0 (hold) ... Cycle 257: en=1 → dut_in=255, expected_out=7, expected_valid=1, done=0 Cycle 258: en=1 → dut_in=0, expected_out=0, expected_valid=0, done=1 (wrap and halt) Cycle 259: en=1 → dut_in=0, expected_out=0, expected_valid=0, done=1 (halted)
{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "en", "wave": "01.01.." },
{},
{ "name": "dut_in", "wave": "======.", "data": ["0", "1", "2", "2", "3", "4"] },
{ "name": "expected_out", "wave": "======.", "data": ["0", "0", "1", "1", "1", "2"] },
{ "name": "expected_valid", "wave": "01....." },
{ "name": "done", "wave": "0......" }
], "head": { "text": "Initial counting sequence with a 1-cycle hold." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset | | en | input | 1 | Enable signal; increments test vector when high | | dut_in | output | 8 | Current test vector; resets to 8'h00 | | expected_out | output | 3 | Expected priority encoder output for dut_in | | expected_valid | output | 1 | Expected valid flag for dut_in | | done | output | 1 | Asserts to 1 when all 256 vectors have been tested |
Constraints
- The reset must be asynchronous and active-low.
expected_outandexpected_validmust be purely combinational functions ofdut_in.- The priority encoder logic must identify the most significant bit (MSB) that is set to 1.
- Once
doneis asserted,dut_inmust remain at 8'h00 anddonemust remain 1 until a reset occurs.
Topics
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