Fast to Slow Domain Data Loss
A data acquisition system transfers burst sensor readings from a high-speed sampling domain to a slower processing domain. The circuit must transfer all valid data words from the fast clock domain (clk_fast) to the slow clock domain (clk_slow) without data loss.
Expected behavior:
When valid_in is high, data_in is captured on the rising edge of clk_fast. The captured data must sequentially appear on data_out with valid_out asserted high on the rising edge of clk_slow. All captured words must be transferred in their original order.
Simulation shows dropped data words during burst transfers. When a burst of four consecutive words is sent on data_in while valid_in is high, data_out only outputs the first word of the burst. The intermediate data words are lost. Inspect the circuit and correct the fault.
Constraints
- The fast clock runs at exactly four times the frequency of the slow clock.
- All transferred words must be properly synchronized to the
clk_slowdomain. - You must not alter the clock generators or the input stimulus.
Topics
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