CodiodeCodiode
Home
Problem Solving
Skill Tracks
My Assignments
Contests
Leaderboard
Community
Settings
Codiode/Problems/Sequential Logic

Four-Bit Register

MediumLogic CircuitBuild

A register is where a datapath remembers: four D flip-flops sharing one clock, capturing a whole operand at once. The bus register packages that idiom into a single component — the storage element you'll instantiate a dozen times in any real design.

Build a 4-bit register: on each rising clock edge, Q captures the value on the bus D. While the clock is low, Q holds. When RST = 1, the register clears to 0.

Constraints

  • Use the Bus Register component from the Buses palette group.
  • D and Q are pre-placed at 4-bit width.

Topics

sequentialregisterbusesclock

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

Sign in to solveSee what Pro unlocks

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Related problems

  • 3-bit Ripple Counter from Toggle Flip-FlopsEasy
  • D Latch from a 2:1 MUXEasy
  • 2-bit Ring CounterEasy
  • T Flip-Flop from a D Flip-FlopEasy
  • Handshake Deadlock Due to Early ResetHard
  • Reconvergence of Individually Synchronized BitsHard
  • Debug: Asynchronous Clear GlitchHard
  • Clock Gate Enable Crossing DomainsHard

Browse all problems · Learning tracks